SpiNNaker - Fascicle Processor

Shown above is a single processing element, or Fascicle, of the SpiNNaker chip. This is engineered around an ARM 968 processor with "Tightly Coupled" instruction and data memories, ITCM and DTCM, sufficient to implement a Fascicle (group of neurons with associated inputs and outputs) of about 1000 simple spiking neurons. Each processing core has a Timer, an Interrupt Controller, a Communications Controller and a DMA Controller to support neural computation. Each processing core also has access, via its DMA controller and an asynchronous System Network-on-Chip (NoC) linking all the cores, to 1GB of SDRAM shared between all cores of the SpiNNaker chip. The SDRAM holds the large volume of information on synaptic connectivity which is pulled into a processing core on demand. Each core also connects to the SpiNNaker chip's Comms-NoC which provides a path into the SpiNNaker chip's "Router" to enable the transmission of data packets either to other processor cores within the chip or to processors of other interconnected SpiNNaker chips via one of the six input/output links of the SpiNNaker chip.